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CMOS Static RAM 1 Meg (256K x 4-Bit) Revolutionary Pinout
Features
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IDT71128
Description
The IDT71128 is a 1,048,576-bit high-speed static RAM organized as 256K x 4. It is fabricated using IDT's high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. The IDT71128 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71128 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.
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256K x 4 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise. Equal access and cycle times -- Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
ADDRESS DECODER
1,048,576-BIT MEMORY ARRAY
.
A17 4 4
I/O0 - I/O3
I/O CONTROL
CS WE OE
CONTROL LOGIC
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FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-3483/09
IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
NC A0 A1 A2 A3 CS I/O0 VCC GND I/O1 WE A4 A5 A6 A7 NC 1 32 2 31 3 30 4 29 5 28 6 SO32-3 27 7 26 8 25 24 9 23 10 22 11 21 12 13 20 14 19 15 18 16 17 A17 A16 A15 A14 A13 OE I/O3 GND VCC I/O2 A12 A11 A10 A9 A8 NC
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Absolute Maximum Ratings(1)
Symbol VTERM TA TBIAS TSTG PT IOUT
(2)
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Value -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.25 50
(2)
Unit V
o o
C C C
o
W mA
3483 tbl 02
SOJ Top View
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V.
Capacitance Truth Table(1,2)
CS L L L H VHC(3) OE L X H X X WE H L H X X I/O DATAOUT DATAIN High-Z High-Z High-Z Function Read Data Write Data Output Disabled Deselected - Standby (ISB) Deselected - Standby (ISB1)
3483 tbl 01
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 8 8 Unit pF pF
3483 tbl 03
NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested.
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C GND 0V 0V VCC 5.0V 10% 5.0V 10%
3483 tbl 04
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 VCC +0.5 0.8
Unit V V V V
3483 tbl 05
NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
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IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
(VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges)
Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
3483 tbl 06
2.4
DC Electrical Characteristics(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71128S12 Symbol ICC ISB Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2) VIN < VLC or VIN > VHC Com'l. 155 40 10 Ind. 155 40 10 71128S15 Com'l. 150 40 10 Ind. 150 40 10 71128S20 Com'l. 145 40 10 Ind. 145 40 10 Unit mA mA mA
ISB1
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
3483 tbl 07
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 and 2
3483 tbl 08
AC Test Loads
5V 480 DATA OUT 30pF 255
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5V 480 DATA OUT 5pF* 255
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Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
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IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V 10%, Commercial and Industrial Temperature Ranges)
71128S12 Symbol READ CYCLE tRC tAA tACS tCLZ (1) tCHZ(1) tOE tOLZ
(1)
71128S15 Min. Max.
71128S20 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time
12
____ ____
____
15
____ ____
____
20
____ ____
____
ns ns ns ns ns ns ns ns ns ns ns
12 12
____
15 15
____
20 20
____
3 0
____
3 0
____
3 0
____
6 6
____
7 7
____
8 8
____
0 0 4 0
____
0 0 4 0
____
0 0 4 0
____
tOHZ (1) tOH tPU
(1)
5
____
5
____
7
____
____
____
____
tPD(1) WRITE CYCLE tWC tAW tCW tAS tWP tWR tDW tDH tOW
(1)
12
15
20
Write Cycle Time Address Valid to End of Write Chip Select to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output active from End-of-Write Write Enable to Output in High-Z
12 10 10 0 10 0 7 0 3 0
____ ____ ____ ____ ____ ____ ____ ____
15 12 12 0 12 0 8 0 3 0
____ ____ ____ ____ ____ ____ ____ ____
20 15 15 0 15 0 9 0 4 0
____ ____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns
3483 tbl 09
____
____
____
tWHZ(1)
5
5
8
NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
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IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS tOLZ
(5) (5) (3)
tACS
tCLZ DATAOUT
tCHZ
(5)
tOHZ (5)
HIGH IMPEDANCE
DATAOUT VALID tPD
VCC SUPPLY ICC CURRENT ISB
tPU
3483 drw 05
Timing Waveform of Read Cycle No. 2 (1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
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NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
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IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
tWC ADDRESS tAW CS tAS WE tWHZ DATAOUT
(3) (5)
tWP (2)
tWR
tOW HIGH IMPEDANCE tDW tDH
(5)
tCHZ
(3)
(5)
DATAIN
DATAIN VALID
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Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATAIN VALID
3483 drw 08
tCW
tWR
tDH
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured 200mV from steady state.
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IDT 71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71128 Device Type S Power XX Speed X Package X Process/ Temperature Range Blank I Y Commercial (0C to +70C) Industrial (-40C to +85C) 400-mil SOJ (SO32-3)
12 15 20
Speed in nanoseconds
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IDT71128 CMOS Static RAM 1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Datasheet Document History
8/5/99 Pg. 3 Pg. 4 Pg. 6 Pg. 8 Pg. 1, 3, 4, 7 Pg. 3 Pg. 3 Updated to new format Removed military entries from DC table Removed Note 1, renumbered notes and footnotes Removed Note 1, renumbered notes and footnotes Added Datasheet Document History Added 12ns, 15ns, and 20ns industrial temperature speed grade offerings Revise ISB for Industrial Temperature offerings to meet commerical specifications Revised ISB to accomidate speed functionality Not recommended for new designs Removed "Not recommended for new designs"
8/13/99 9/30/99 2/18/00 3/14/00 8/09/00 02/01/01
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for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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